Non-volatile memory devices are capable of storing data even when the power is turned off. Because of this characteristic, non-volatile memories may be used in a wide variety of applications in new portable storage media. FLASH memory devices having a floating gate have been widely used in a field of non-volatile memory devices. Specifically, FLASH memory devices with a stacked gate structure have been used because they may be formed using a relatively simple process. A unit cell of a FLASH memory device with a stacked gate structure may comprise a sequentially stacked structure including a tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode. The unit cell may further comprise source/drain regions that are arranged in a substrate at both sides of the floating gate. The floating gate is electrically isolated. The data stored in the FLASH memory cell may be a logic “1” or “0” depending on charges in the floating gate.
Charges in the floating gate are stored in a “free-charge” state. Accordingly, if a tunnel oxide layer under the floating gate is partially damaged, then all charges stored in the floating gate may be lost. For this reason, a FLASH memory cell having a floating gate may require a tunnel oxide layer with sufficient thickness.
If the thickness of the tunnel oxide layer increases, a reliability of the FLASH memory cell may be improved; however, an operation voltage may increase. As a result, a peripheral circuit part (for controlling high voltage) of the FLASH memory device may become more complex. Second, power consumption of the FLASH memory device may increase. Third, an operation speed of the FLASH memory device may decrease. To overcome one or more of these problems, a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) configuration has been suggested.
A general MONOS memory cell is disclosed in U.S. Pat. No. 6,103,572. According to FIG. 23 of the U.S. Pat. No. 6,103,572, the MONOS memory cell includes a tunnel oxide layer, a silicon nitride layer, a top oxide film and a gate electrode, which are stacked sequentially on a substrate. High-concentration diffusion regions are placed in the substrate at both sides of the gate electrode, respectively. The high-concentration diffusion regions correspond to source/drain regions.
The MONOS memory cell stores charges in the silicon nitride layer. In other words, the silicon nitride layer has deep level traps, and charges are stored in the deep level traps. Accordingly, even if the tunnel oxide layer is partially damaged, the MONOS memory cell may lose a part of the charges in the silicon nitride layer. Therefore, it is possible to form a tunnel oxide layer thinner than the FLASH memory cell having the floating gate. As a result, the MONOS memory cell uses a relatively low operation voltage in comparison with the FLASH memory cell. That is, in comparison with the FLASH memory cell, the MONOS memory cell may have lower power consumption and improved operation speed.
In another approach, even if the MONOS memory cell uses a relatively low operation voltage as compared to the FLASH memory cell, it uses high operation voltages rather than the power voltage. Accordingly, a MONOS memory device having a MONOS memory cell typically has a high-voltage MOS transistor (hereinafter referred to as a high-voltage transistor). In addition, the MONOS memory device may include a low-voltage MOS transistor (hereinafter referred to as a low-voltage transistor) where a low voltage is applied. The low and high voltage transistors may require a gate insulation layer different from a gate insulation layer of associated with the three-layered structure of the MONOS memory cell (e.g., a tunnel oxide layer, a silicon nitride layer and a top oxide layer). The reason for this is that if the gate insulation layer with the three-layered structure is used as a gate oxide layer of the low and high voltage transistors, problems may exist with the low and high voltage transistors. For instance, in the low and high voltage transistors, a threshold voltage of the low-voltage transistor may be changed by soft programming. As a result, various turn-on currents of the low-voltage transistor may induce leakage current.